This application is based upon and claims priority from prior French Patent Application No. 99-12381, filed Oct. 5, 1999, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention generally relates to the field of analog and digital integrated circuits, and more particularly to a process for obtaining an adjustable electrical resistance applied to an integrated circuit component.
2. Description of the Prior Art
In actual fact, the applicant has noticed that the accuracy which is excellent during the step of sorting the silicon wafers, that is to say of eliminating wafers exhibiting defects, may be degraded during the subsequent encapsulation step. By way of example, for an operational amplifier, during the sorting of the wafers one may find offset voltages of the order of 2 mV which, after adjustment, are reduced to 1 mV. In actual fact, encapsulation by insertion into a package creates additional drifting which modifies the final offset voltage to 1.5 mV. For a voltage reference or a voltage regulator, when sorting the wafers, the accuracy is 0.8%, modified to 0.2% after adjustment. As in the case of the amplifier, a drift which modifies the final accuracy to 0.5% is introduced on insertion into the package.
Additionally, these circuits must use the smallest possible area of silicon so as to cut costs while retaining high accuracy which has been problematic in the past.
Accordingly, there exists a need for overcoming the disadvantages of the prior art as discussed above.
According to a preferred embodiment of the present invention, a preferred implementation will remedy the drawbacks of the prior art as discussed above. A preferred embodiment of the present invention proposes to adjust integrated circuits after they have been inserted into their package, especially the standard integrated circuits produced in large batches at low cost. The aim is to obtain very high accuracy, at least equal to that obtained after adjustment during the sorting of the wafers.
The process, according to the invention, is intended for obtaining an adjustable electrical resistance, in which a first voltage is applied to an integrated MOS transistor on its source, its gate and its substrate, and a second voltage is applied on its drain, the first and second voltages being able to initiate a breakdown of the MOS transistor by:
avalanche of the drain/substrate junction,
biasing of the parasitic bipolar transistor of the MOS transistor,
irreversible breakdown of the drain/substrate junction,
shorting between the drain and the source.
Advantageously, the electrical resistance obtained is adjustable in a unidirectional manner, its value being determined by the current due to the first and second voltages and being modifiable by application of other voltages with a higher current limitation, the first and second voltages being provided by a generator with current limitation.
In one embodiment of the invention, one of the first and second voltages is constant, and the other voltage is a monotonically varying ramp.
In one embodiment of the invention, the application of the first and second voltages takes place before a step of encapsulation of a circuit of which the MOS transistor forms part.
In another embodiment of the invention, the application of the first and second voltages takes place after a step of encapsulation of a circuit of which the MOS transistor forms part. The control of the breakdown of the MOS transistor can be effected via the conventional pins of the integrated circuit: ground, power supply, input(s), output(s).
A preferred embodiment of the present invention provides an integrated active electronic component, comprising a MOS transistor. The MOS transistor is caused to break down by avalanche of the drain/substrate junction, biasing of the parasitic bipolar transistor of the MOS transistor, irreversible breakdown of the drain/substrate junction, and shorting between the drain and the source, in such a way that the component forms an adjustable resistance of value determined by the current due to the voltage difference between the drain and the source of the MOS transistor.
According to a preferred embodiment of the present invention, an electronic circuit comprises at least two components of the type described above so as to form a bidirectionally adjustable electrical resistance.
In one embodiment of the invention, the electronic circuit comprises a MOS transistor, a first component of the type described above, arranged in parallel between the drain and the source of the MOS transistor, a second component of the type described above, arranged between the gate of the MOS transistor and ground, and a current source arranged between the gate and the power supply.
The invention therefore makes it possible to propose standard integrated circuits of increased accuracy. The use of so-called xe2x80x9csnap-backxe2x80x9d MOS transistors makes it possible to obtain shorting and hence to vary a resistance inside an integrated circuit after its encapsulation by acting on the conventional pins of the integrated circuit. The component thus produced occupies little room on a silicon wafer in the sense that it comprises just a single MOS transistor. The fact that the gate and the source of the MOS transistor are short-circuited guarantees that it is permanently off and prevents it from influencing the operation of the adjacent electronic circuits.
The invention harnesses a natural characteristic of MOS transistors, namely that they possess parasitic components, in particular a bipolar transistor. In certain configurations, these parasitic components are harmful. During electrostatic discharges, circuits may be seriously damaged by the turning on of the parasitic transistor. Conversely, the invention uses the parasitic bipolar transistor of the MOS transistor to cause shorting thereof and to vary the resistance between the drain and the source of the MOS transistor, that is to say between the collector and the emitter of the parasitic bipolar transistor.